The present disclosure relates to a method of annealing metal interconnect structures employing nanosecond-scale laser irradiation.
Generally it is desirable to provide a copper interconnect structure in which copper grain size is large and residual stresses, seams, and voids are minimized within the copper interconnect structure. A typical copper interconnect anneal is conducted in a batch furnace at temperatures of less than 200° C. for several hours. Copper has a high plasticity even at such moderate temperatures. Superior copper plasticity coupled with a long anneal time is enough to reflow interconnects, relieve residual stresses, and to grow the grains. In addition to a dedicated copper annealing, formed copper wires are inadvertently annealed at about 375° C. for tens of minutes during depositing/curing subsequent insulating layers. Modern integrated circuits have multiple (up to 15-20) layers of copper interconnect levels. The bottom interconnect layers are affected by thermal treatments of subsequent interconnect layers resulting in additional copper grain growth in the bottom interconnect structures.
A wire resistivity reduction is typically associated with increased copper grains. Reduced electron scattering off the grain boundaries is responsible for this resistivity reduction. Accordingly, the reduction will be observable in both wide and thin copper wires where the average grain size increases from below to above, or about, the mean free path of free electrons in copper (˜40 nm) and, more preferably, to above twice the mean free path of free electrons (˜80 nm). In addition, copper deposition techniques promote textured (111) copper grains known as the bamboo or columnar grain structure. The bamboo grain structure exhibits less grain boundary scattering in the direction of current flow and is considered to be highly preferred.
Lateral and vertical scaling of copper interconnects to beyond about 80 nm or twice the mean free path of free electrons in copper leads to a nonlinear rise of copper wire resistance known as the interconnect size effect. The size effect becomes the dominant constraint on both interconnect scaling beyond about 40 nm and overall integrated chip (IC) performance due to much increased resistance of thin wires and narrow vias. The primary physical mechanism behind the size effect is the electron scattering off the interconnect interfaces. Interconnect interfaces may exhibit different types of electron scattering: diffused scattering and specular scattering. Diffused scattering is responsible for the nonlinear rise of copper wire resistance while the specular scattering does not affect wire resistance. Engineering copper wire interfaces is directed toward increasing specular scattering component over diffused scattering component.
Improving resistance of an integrated line and via structure within copper interconnect structures having widths less than, or on the order of, the mean free path of free electrons in copper has been notoriously difficult because high temperature anneal processes intended to decrease the resistance of the line portion of the integrated line and via structure tends to create voids near the via structure, thereby increasing the resistance of the via structure. The positive correlation between the size of Cu grains after an anneal process and frequency of a “copper pull” from a via structure to form a cavity is well known in the art.